The present invention relates to clock circuits for integrated circuits generally, and more particularly to circuits for improving the duty cycle of clock signals on integrated circuits.
Digital and mixed signal integrated circuits use clock signals to transfer data from one circuit block to another, to time data, to ensure that data flows through the chip in an orderly sequential manner, and for other purposes.
The duty cycle of these clock signals should generally be close to 50 percent to ensure optimum circuit performance. That is, for each cycle, the clock signal should be at a logic low level and a logic high level for nearly equal durations. This promotes reliable clocking of circuits and their data. A clock signal having a duty cycle that deviates far from 50 percent may have such short high or low times that the clock signal is not seen by a circuit being clocked. Also, some circuits transfer data on each edge of a clock signal, that is, on each rising and falling edge. Other circuits clock data on a rising edge but communicate with another that clocks data on the falling edge—if the edges are too close data may not transfer from one circuit to the next.
The duty of a clock may become distorted by many circuit phenomena. For example, the edge rates provided by a driving circuit may be mismatched due to process variations or other mismatches. That is, a clock driver may provide rising edges that are faster that its falling edges. Also, the trip point or threshold may not be centered for a driving circuit that is receiving and amplifying a clock signal. Capacitive loading and inductive effects can also distort a clock signal's duty cycle.
Traditional solutions include circuits such as phase-locked loops that can recover or regenerate a clock signal's duty cycle. But these circuits are large and tend to consume a great deal of power and die area.
Thus, what is needed are circuits, methods, and apparatus for recovering or regenerating a clock signal's duty cycle without the use of complicated circuitry.